1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a structure of a lateral MOSFET and a method of manufacturing the same.
2. Description of the Related Art
Power MOSFETs include a LDMOS (Lateral Double diffused MOS) transistor as well known. The LDMOS transistor has a lower on-resistance and a smaller parasitic capacity and accordingly is hopeful as a low-breakdown voltage power device used for a synchronous rectifier.
A middle- or high-breakdown voltage LDMOS transistor of the conventional art depletes a drift region (resurf layer) formed in a region between a gate and a drain layer to retain the lateral breakdown voltage. The LDMOS is supplied with a gate drive voltage lower than the device breakdown voltage in many cases. though, on the application of a reverse bias, the drift region is depleted and accordingly a high voltage is never applied to the gate oxide film.
On the contrary, in a lower-breakdown voltage device with a drift region designed shorter, the device breakdown voltage can be retained without completely depleting the drift region. Therefore, on the application of a reverse bias, most of the reverse bias voltage is applied across the gate and the drift region, and a voltage higher than the gate drive voltage may be applied to the gate oxide film possibly. A CMOS has no such problem because the device breakdown voltage is designed equal to the gate drive voltage.
In recent years, fine patterning processes and fine patterning design rules similar to those for CMOS transistors, such as a 0.35 μm-rule and a 0.15 μm-rule, have been increasingly applied also to the LDMOS transistors. The application of the fine patterning design rule makes it possible to realize a short-channel LDMOS transistor and design a low-voltage driven LDMOS transistor. In such the case, a circuitry design can be realized for combining fine-patterned CMOS transistors with LDMOS transistors.
On the other hand, as regions are patterned finer, a mask misalignment greatly influences. The fine patterning process includes execution of a corresponding high-precision mask alignment though it is impossible to eliminate the mask misalignment completely. Therefore, a much finer patterning design may enlarge the region influenced by the mask alignment precision such as the estimation of a design margin.
As described above, the drift region in the LDMOS transistor is a region that most influences on the device breakdown voltage. In the case of a drift length of several μm, the mask misalignment influences less. In a design for a low breakdown voltage such as a breakdown voltage of around 5 V, the drift length is made extremely short such as 0.1-0.2 μm, which is greatly influenced by the mask misalignment. Thus, there is devised a method of implanting ions separately into the drift region with a mask of a sidewall having a width of 0.1-0.2 μm around the gate electrode (for example, JP 2005-116892A).
In the LDMOS transistor having the gate supplied with the drive voltage set lower than the source-drain breakdown voltage as described above, however, a higher dose to the drift region allows the electric field to concentrate between the gate and the drift layer on the application of a reverse voltage across source-drain. In this case, the voltage across the gate end and the drift layer exceeds the gate drive voltage and may possibly destruct the gate and cause a loss of the device reliability.